8086 is a 16-bit microprocessor and address bus of 20-bit size. In this tutorial, we will see internal architecture of 8086 microprocessor. Firstly, we will discuss bus interface unit part and secondly, we will discuss execution unit part along with details of general purpose and special function registers.
8086 Introduction
In 1978, Intel introduced the x86 instruction set architecture (ISA) which was the successor of the 8088 microprocessors. It was the first microprocessor-based computing architecture developed in the IA family. After that, Intel developed other microprocessors like 80186, 80286, 80386, Core 2 and Pentium series, etc. All these were the successors of the 8086 processor.
They are almost internally similar with slight variations in the data bus, address space, and memory addresses. The x86 architecture describes the way how instructions are passed from a software program to the operating system and the process of their execution. It is a 16-bit machine with a wider data path of 16-bits and 20 address lines which means it can access 2^20 = 1024k – 1MB of memory. Therefore, it has an addressable memory of 1 MB.
Some other useful features are:
- Operates in two modes of operation such as maximum and minimum (will discuss int later sections of this tutorial)
- Implements basic pipelining feature by using 6 bytes instruction queue
- Operates on +5 Volts
- 40- Pin package
- Byte addressable memory
Intel 8086 Architecture main Units
The x86 architecture consists of two main units. The first one is the execution unit (EU). It is responsible for executions of instructions. It has an arithmetic logic unit (ALU) which performs arithmetic and logical operations on data.
The second one is the Bus Interface Unit (BIU). It is used to perform memory read-write operations, I/O read and to transfer data between memory and I/O devices.
These two units (EU and BIU) are interlinked through a 6 bytes instruction queue.
Now lets first discuss the Bus interface unit in detail.
8086 Bus Interface Unit
BIU contains segment registers and an instruction pointer. It accesses memory by combining data information and address to generate a 20-bit physical address. This 20-bit long physical address is used to access the memory location. Some other functions of BIU include fetching of instructions from memory, transfer of data from and to the memory. Followings are the main functions of BIU:
- Instructions feteching
- 20-bit address generation to access memory
- Data transfer operation between memory and I/O devices
- 6 bytes prefetch instruction queue management
Segment Registers
BIU consists of six segment registers, the instruction pointer, and each register is of 16-bit width. They act as pointers used for selecting the particular segment in memory. BIU also contains an address generation circuit.
Note: Don’t confuse segment registers with memory segments of the program, memory segments are actual segments of the memory where your code and program data store. On the contrary, segment registers are used to hold addresses of different memory segments.
Now lets discuss the function of each segment register.
Code Segment Register (CS)
The code segment of program memory has all the code instructions. The code segment register stores the base address of the code segment.
Data Segment Register (DS)
The data segment contains the data of the program and this register holds the base address of the data segment.
Stack Segment Register (SS)
The stack segment of program memory contains return addresses, input parameters, return values of function calls. The stack segment register stores the starting addresses of the stack segment. The value of the stack segment register is added to an offset value to access any location within that segment.
Extra Segment Register (ES)
The Extra Segment (ES) register provides additional storage. In 80386 microprocessors, two additional segment registers were added which are Far Segment Register (FS) and Global Segment register (GS) which allows the memory access up to 6x64KB= 384K bytes. ES register holds the base address of the extra segment.
Instruction Pointer (IP)
The IP register is a 16-bit register which contains the address of the next instruction to be executed. Instruction pointer values get incremented automatically after every instruction is executed. In 80386 and the latest versions, the size of this register is extended to 32-bits and is known as the EIP register. You cannot change the content of this register or access it directly. Only instructions like branching, jump, loops, interrupts or stacks-related instructions can change the IP.
Address Generation Circuit
The BUS interface unit also contains an address generation circuit that helps to generate the address of the next instruction that we want to execute. This circuit generates a 20-bit physical address by combining code segment register value and the current value of instruction pointer.
The address of next instruction to be executed is given by this foumula:
IP (next value) = CS x 10H + IPWhere CS is code segment register value and IP is current value of instruction pointer.
Prefetch Queue ( Pipelining)
8086 microprocessor implements basic pipelining with the help of 6 bytes prefetch queue. This is a first-in-first-out queue. It fetches the next instruction from the code segment at the same time the execution unit executes the current instruction. The fetching and executing stage works in parrel. Hence, 8086 supports 2 steps pipelining.
Note: Both pipelining stages get flushed whenever branch instructions occur.
8086 Microprocessor Execution Unit
As metioned earlier, the second main unit of 8086 microprocssor is a execution unit which consists of following main components:
- Arithmetic and Logic Unit ( ALU)
- 16-bit General Purpose Registers
- 16-bit Special Purpose Registers
- Instruction Register
- Instruction Decoder Circuit
- Flag/Status Register
It has a 16-bit wide data bus and internal registers of 16 bits size. Thus, it can access and work on 16-bits data at a time. For writing code in assembly language, you should know about the registers as they are temporary storage sources for data to perform arithmetic and logical operations.
General Purpose Registers
8086 execution units consists of four general purpose and four special function registers as shown in figure below:
The programmers use general-purpose registers for performing arithmetic computations, logical operations, data storage & pointers to memory.
The 8086 architecture consists of 4 general-purpose registers of 16 bits. such as AX, BX, CX, and DX. You can access any register depending upon the size of your data. All registers have dedicated functions. The accumulator register (AX), Base Register (BX), Counter Register (CX), and a data register (DX) are of 16 bits each.
They can also be treated as an eight-bit register. These registers are divided into two parts. For example, AX has two parts AH (first 8 most significant bits) and AL (lower 8 bits). The microprocessors 8086, 8088 and 80286 are 16-bit machines. The size of registers in microprocessors 80386 and 80586 has extended to 32-bits.
Note: In modern 64-bit Intel processors, the registers are of 64-bits size which are RAX, RBX, RCX, and RDX.
The 32-bit registers are only available in 80386 architecture and above. In addition to the above-mentioned functions, all these registers have some special functions.
Accumulator Register (AX)
Accumulator register holds values of arithmetic operations like multiplication, division, etc. For example, it holds values of operands or output of arithmetic operations.
Base Register (BX)
Base register (BX) holds the base address of the program such as offset address in indirect addressing mode.
Counter Register (CX)
s the name implies, the count register (CX) counts the number of iterations in loops, and in strings operations, it specifies the number of characters in a particular string.
Data Register Register (DX)
The data register holds overflow and I/O addresses. Moreover, it is used in combination with AX register to store 32-bit results of multiplication and division.
Special Function Registers
The x86 architecture has four special function registers namely, base pointer (BP), stack pointer (SP), source index (SI), and destination index (DI) registers.
SP Register
This register is usd to hold the top of the stack segment address. It helps to keep track of stack elements and we perform PUSH, POP operations by using stack pointer value.
BP Register
BP can hold the address of any location within a stack segment and unike SP, we can use base pointer to access element from stack from any location. But, we can also use BP to access data from other sections/segments of a program.
In short, the Base Pointer (BP) and Stack Pointer (SP) registers are used when dealing with stacks especially function calls and returns. The stack pointer points to the top of the stack whereas BP is used to move within the stack.
SI & DI Registers
Index registers (SI & DI) are particularly useful to perform string operations. They are mainly used in string operations for storing the source and destination addresses of operands. The source index register contains offset address of the data segment during string operation. Similarly, the destination index register contains an offset address of the extra segment during string operation.
Note: SI and DI also use to access elements of an array.
Flag Register
It is a 16-bit status register which indicates the state of the processor. Some of its bits are reserved, hence only a few bits are used. It has six conditional flags and three control flags.
Bits with symbol “U” are unused and “R” are reserved bits. Whenever an instruction is executed and produces a result, it may modify some bit(s) of the FLAGS
8086 CONDITIONAL FLAGS
As the name implies, conditional flags indicate a condition. They sets to 1 and 0 depending upon the condition of result produced as a result of arithmetic instruction.
- Carry Flag (CF)
It is set to 1 if the last operation produced an extra bit beyond the size of register or borrowed a bit thus increasing the size of the register.
- Parity Flag (PF)
In some operations, the lower byte of result is checked. If it is an even number of multiple of 2, PF is set to 1.
- Adjust Flag (AF)
The AF Flag is used in BCD arithmetic instructions. This flag is set to 1 if the 1-byte arithmetic operation generates a carry from bit 3 into bit 4.
- Zero Flag (ZF)
The sixth bit of flag register is set to 1 if an arithmetic operation generates Zero result.
- Sign Flag (SF)
It indicates the sign of the result produced by checking the leftmost bit. A positive result sets the SF flag to 0 and negative result sets it to 1.
- Overflow Flag (OF)
Sets to 1 if the value of result produced is too large for the register.
8086 CONTROL FLAGS
The control flags are used to control the instructions. These are:
- Trap Flag (TF)
It is set to 1 in case of step by step debugging allows only one instruction to execute at a time.
- Interruption Flag (IF)
It enable or disable internal and external interrupts requests. When it is set to 1, the interrupts are enabled and vice versa.
- Direction Flag (DF)
The DF selects increment or decrement mode for SI and DI registers in string operations. These registers decrement when DF is set to 1 and vice versa.
8086 Microprocessor Memory Model
This topic discusses the basic memory model of x86 processor architecture. The 8086 processor has a 16-bit data bus and 20-bit address bus. After that, Intel introduced 80186, 80286, 801386 and many other versions. The 8086 processor architecture consists of a 1MB byte addressable segmented memory model.
Program Memory Segments
The segmentation allows processors to address four segments of 64KB. One memory address holds 1 byte of data. Two bytes need two memory addresses for storage and so on. It has a little-endian architecture i.e. the least significant bit is stored at the lowest address and most significant bit at the higher address.
The memory is divided into segments. Code, data and stack have independent segments. All these segments operate independently of each other. Every program has a logical address consisting of two parts i.e., a segment selector which identifies segments and an offset for identifying a byte in that segment.
Segmented memory model allows easy implementation of object-oriented programs. Two processes can easily share data through segments. Let’s suppose you want to store in a variable num. It would be represented in memory as:
| 35 | 24 | 5C | A1 |
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thank you
that was very useful.