input output ports of dspic30f2010 microcontroller

This article offers information on the Input and Output ports for the dsPIC30F2010 group of gadgets. The greater part of the dspic30f2010 microcontroller is that pins are shared between the peripherals and parallel I/O ports but except of VDD, VSS, MCLR, CLKI/OSC1 ports.In it most of the I/O pins are getting multiplexed with exchange functions. This multiplexing will rely upon the marginal features on the gadget variation. The universally useful I/O ports permit the dsPIC30F2010 to watch and control different devices.  By and large, when a marginal feature is working that stack/pin may not be utilized as a broadly useful I/O stack.

At the point when a peripheral is empowered and the marginal feature is currently driving a related pin and the utilization of the pin as a universally useful yield pin is impaired. The input and output pin might be perused, however, the yielding or output driver for the parallel port the bit will be debilitated. In the event that a peripheral is empowered but that pin might be driven by a port but it is not able to drive by pin.

dspic30f2010 input output ports registers

Every single port stick have three registers specifically related with the activity of the port stick. These three are:

  1. TRISx  (Data Direction register)
  2. LATx (I/O Latch register)
  3. PORTx (I/O Port register)

Every input and output pin upon the device has a related bit in the TRIS, PORT, and LAT.

TRIS Registers:

The information course enlist (TRISx) decides if the pin is an input or on the other hand a output. On the off chance that the information heading bit is a ‘1’, at that point the pin is information. Every single port pins are characterized as input after a Reset.

LAT Registers:

The LATx register related with an I/O pin just to clear the problems that might occur with read-modify-write instructions. Peruses from the register (LATx) revenues the values held in the port output keys but not the values return on the I/O pins. Keeps in touch with the lock, compose the hook (LATx). Peruses from the port (PORTx), and writes to the port pins, compose the hook (LATx).

PORT Registers:

Information on an Input and Output pin is edited via a PORTx register. A read of the PORTx will read the instruction or value of the I/O pin, while compose to the PORTx will write the instruction to the port data latch.That implies the comparing LATx and TRISx registers and the port stick will read as zeros.

At the point when a stick is imparted to another peripheral or capacity that is characterized as an info just, it is by the by viewed as a committed port in light of the fact that there is no another contending wellspring of yields. An illustration is the INT4 pin. And a parallel I/O port (PIO) that offers a pin with a peripheral is, by and large, subservient to the fringe. The peripheral’s yield support information and control signals are given to a couple of multiplexers. The multiplexers select whether the fringe or the related port has responsibility for yield information and control signs of the I/O cushion cell.

Configuring Analog Port Pins

The analogue pins is controlled by two registers named ADPCFG and TRIS in which TRIS is bit set (input) and if it is cleared, then the digital output level (VOH or VOL) would be converted. The configuration of pins as digital inputs would not be converted as an analogue input. Any pin which is characterized as a digital input might be became cause of the input barrier just to consume current which is cause of the surpasses the device characterization. Its writing timing or one data cycle timing is between a port direction change or port write operation as well as the read at the same port.

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