74LS164 Serial In Parallel Out Shift Register IC

74LS164 is a high speed shift register with serial input of data and parallel output of data. It is an 8-bit IC. That means data goes into IC bit by bit serially and 8-bit data appears on the output pins. Data at serial input is fed through 1 input AND gate and it is synchronous with LOW to HIGH transition of the clock. In other words, the transition of data occurs on every positive edge of the input clock. 

It is also referred with these names such as SN54164, SN54LS164, SN74164, SN74LS164

Pinout Details

The following figure shows the pinout diagram of the 74LS164 IC. As you can see it is a 14 pin IC and it is available in different package formats. 

74LS164 pinout

Pin Configuration Details

The detailed description of 74LS164 shift register IC pins is given below.

  • A, B : These pins are used to input serial data to IC which needs to be converted into parallel output. In other words, these are serial data input pins. 
  • CP : This input pin is for a clock signal. It is an active high rising edge pin.
  • ~MR :  This pin is used to perform the function of master Reset. This is an active low input pin. Signal at this pin independent of clock, sets all outputs to LOW and clears the register.
  • Q0 – Q7 :  These are output pins and used for providing parallel data of 8 bits as output.
  • VCC = This is +ve terminal for feeding power supply.
  • GND = This is the ground terminal of power supply.

Internal Logic Diagram

The logic diagram of the 74LS164 shift register IC is shown in the figure below. It internally consists of 8 flip flops, one AND and two Not gates. 

interal logic diagram

Truth Table

The Truth Table for working of IC is shown in the figure below.

74LS164 truth table

Equivalent ICs: 74LS165, 74LS166, 74LS170, 74LS295

74LS164 Shift Register Working

Following is the working of this particular IC.

  1. ~MR is an active low input master reset pin. Until its state is low, no matter what is at input A or B, the output will be in a low state. So it may be called Reset or clear mode of operation. In order to perform operation ~MR must be set high.
  2. A and B are two input pins and serial data can be fed through any one of the two input pins while using another pin as an active high enables for data entry to other input pins. Any input pin which is not being used must be set to High. It is also possible to connect two input pins together.
  3. When any transition of a clock from low to high occurs, Data is shifted one place towards the right and Q0 is filled with AND of two data inputs at A and B. 

Data Transition on Output Pins

  1. When A = B = High. Q0 will be High and data will be shifted towards right by one place. For example, if before transition of clock, data was Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = a b C D E F G H. Then after clock transition output will be Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = 1 a b C D E F G. Here a and b can be in any state 1 or 0.
  2. At A = High and B = Low. Q0 will be low and data will be shifted towards right by one place. For example, if before transition of clock, data was Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = a b C D E F G H. Then after clock transition output will be Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = 0 a b C D E F G. Here a and b can be in any state 1 or 0.
  3. When A = Low and B = High. Q0 will be low and data will be shifted towards right by one place. For example, if before transition of clock, data was Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = a b C D E F G H. Then after clock transition output will be Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = 0 a b C D E F G. Here a and b can be in any state 1 or 0.
  4. At A = Low and B = Low. Q0 will be low and data will be shifted towards right by one place. For example, if before transition of clock, data was Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = a b C D E F G H. Then after clock transition output will be Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = 0 a b C D E F G. Here a and b can be in any state 1 or 0.

74LS164 Proteus Simulations

Working of IC can be verified from Simulations in Proteus Software. Following is the small description of these simulations.

R (~MR) is active low so until pin 9 is in a low state, reset function is performed and no matter what is at input pins, it does not respond to any input.

74LS164 proteus simulation 1
74LS164 proteus simulation 2

When A = High, B = Low,  A & B = Low, Q0 = 0 and it appears at output at clock pulse.

74LS164 proteus simulation 3

When A = Low, B = High,  A & B = Low, Q0 = 0 and it appears at output at clock pulse.

74LS164 proteus simulation 4

When A = High, B = High,  A & B = High, Q0 = 1 and it appears at output at clock pulse and other bits shift towards right.

74LS164 proteus simulation 5

When A = Low, B = Low,  A & B = Low, Q0 = 0 and it appears at output at clock pulse.

74LS164 proteus simulation 6

Shift Register IC Ordering Code

This IC comes in with three variants as shown in the figure below. The ordering format for these is as follows.

  • SN54LSXXXJ
  • SN74LSXXXN
  • SN74LSXXXD

XXX=164 and J represents that it is made up of ceramic. N represents it comes in plastic casing and D is SOIC packaging.

Features

Following are the distinguished features of 74LS164:

  1. Asynchronous master reset function which means independent of clock pulse it can reset all output pins to LOW.
  2. Transfers data to output pins which are fully synchronized (at a common instant).
  3. High-speed termination effect is limited using Schottky Diodes.
  4. It has the capability to handle electrostatic discharge with more than 3500 V.
  5. 35 MHz typical operating shift frequency.

Applications

  • Digital up and down counters
  • Left and Right shift operations on data
  • Data conversion
  • Arithmetic logic unit
  • Serial and parallel data conversion
  • Sequence generator circuit

Alternative Shift Registe IC’s:

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