Difference between RISC and CISC

The CPU has different sorts of architecture. It utilizes the capacity to work from “Instruction Set Architecture” to where it was first designed. There are two types of this architectural design; RISC (Reduced instruction set computing) and CISC (Complex instruction set computing). Both differ in various ways. RISC is a design of Central Processing Unit that has the basis of basic instruction set. It performs really well when it is used along with a microprocessor system. It has the ability to execute the commands with the help of some microprocessor cycles per command. On the other hand, CISC has the ability to execute a number of steps of single operation or various modes of addressing that are a part of a single set of instruction. It depends on the design of the CPU where a single instruction works a lot of low-level acts. For example, loading from memory, storage into memory and an arithmetic calculation. CISC is the hardware part of the Intel and RISC is Apple hardware.

RISC Architecture

The word RISC is abbreviated as ‘Reduced Instruction Set Computer’. It is such a design of the CPU that follows simple instructions and is really speedy. Basically, it is a subset of a number of instructions. In simple words, each command is supposed to carry out really simple and small jobs. In such a computer, the set of instructions is simple and easy to implement. Therefore, it becomes easy to implement such commands that are really complex and difficult to execute as single instructions. Every instruction is of almost the same length. They are then used together when compound jobs are to be performed with one operation. Normally, each command is to be performed in one machine cycle.RISC Architecure

This method is called pipelining which is mainly used to increase the speed of the RISC machines. It is a very crucial technique. Reduced Instruction Set Computer is a Architecture which is designed in such a way that it carries out only a few commands in parallel simultaneously. Due to the small size if the instructions, the chips used in this sort of architecture need a very few number of transistors. In RISC very less decoding is required. Plus, the data types in the hardware are also less. The general purpose register is the same one for all. The instruction set is uniform. And the addressing nodes are really simple. Finally when a job is being performed, RISC saves the number of cycles in which it is being executed by eliminating the unnecessary part of the code.

Characteristic of RISC

There are a lot of characteristics related to the RISC architecture, some of them are as follows:

  1. Simple set of instructions which are easy to decode and implement.
  2. The size of one instruction comes under the size of a single word.
  3. Only one clock cycle is required to execute a single instruction, so it is a fast process.
  4. The quantity of general purpose register is greater.
  5. The addressing modes are quite simple.
  6. The variable data types are very less.
  7. Its main idea is to achieve pipelining.

Example  Let’s suppose we are to perform addition operation on two 8-bit numbers:

The load command will be used to load the data in the registers and then the addition operator will be used on them and the result will be stored in the location of the output.

CISC Architecture

The word CISC is abbreviated as ‘’Complex Instruction Set Computer’’. It is such a design of the CPU that executes a job using only a single command. The command contains multi-step operations which are to be executed. Moreover, CISC machines have relatively smaller programs. Whereas the number of compound instruction size is huge and so it requires a lot of time in execution. In this type of architecture, each instruction set is very well protected in various steps. This means that there are extra three hundred instructions related to each set of instruction. Due to this, the instructions take time in their execution. Their time may vary from two to ten machine cycles, depending on the size of the instruction set. Furthermore, CISC architecture doesn’t implement pipelining normally as it is hard to.CISC Architecture

If we see from the respect to the compilers, CISC machines have good acts because the range of innovative instructions are easily obtained in a single instruction set. They execute the compound instructions in only a single and complex set of instructions. CISC is able to get processes at low-level. So, it is easier this way to have addressing nodes that are huge and a lot of different data types in machine hardware. Despite of all this CISC works less efficiently than the way RISC works. This is mainly because CISC is unable to remove the portion of the code that is not required and so a lot of cycles are wasted by them when the instruction set is executed. Plus, their microprocessor chips are very difficult to manufacture and program. They are really complex.

Characteristic of CISC

There are a lot of characteristics related to the CISC architecture, some of them are as follows:

  1. The instruction set is complex and so is its decoding.
  2. Instructions are normally large due to their complexity and are normally bigger than one word size.
  3. Usually, the compound instructions take greater time than a single clock cycle in their execution.
  4. The number of general purpose register is less because most of the operations are executed in the memory itself.
  5. The addressing modes are normally complex.
  6. The data types are numerous.

Example – Let’s suppose we are to perform addition operation on two 8-bit numbers:

Only one instruction is used for the execution of this operation. The ADD operation will simply perform the required task. All the tasks will be done by this single command.


This very equation is normally used to check the performance of any computer:RISC vs CISC

This formula clearly tells that the performance of a RISC based architecture is way better than the one operating using CISC architecture. CISC and RISC are two entirely different types of computer architectures. Some of their differences are as follows:

Comparison chart

Memory unit is present to implement the instructions There is no memory unit and registers are used to store data
It is microprogramming unit It has a complex design of compiler
Its compiler design is easy Its compiler design is complex
Its calculations are slower yet precise Its calculations are faster
Their decoding is difficult Decoding of its instructions is easier
Instructions are complex so it takes time in execution It is faster as its instructions are simple
External memory is a requirement No external memory is required
Pipelining is difficult to implement Pipelining is implemented
Their processors often stall There is no stalling normally
Code expansion is easier The expansion of code can be an issue
Disk space is wasted The disk space is saved
Its examples include:

include VAX, PDP-11, Motorola 68k and your desktop PCs

Its examples include:

DEC Alpha, ARC, AMD 29k, Atmel AVR, Intel i860, Blackfin, i960, Motorola 88000, MIPS, PA-RISC, Power, SPARC, SuperH, and ARM

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