# Flash ADC: Explained with 3-bit Flash Analog to Digital Converter Example Circuit

Flash analog to digital converter is the fastest type of ADC among all the other ADCs. It is also known as a parallel analog to digital converter. It comprises high-speed comparators, resistive voltage divider circuits along with a priority encoder. The tutorial is a complete guide that includes its working, advantages, disadvantages, and its applications in the market.

An N-bit flash ADC consists of 2 powered N-1 comparators and contains 2 powered N number of matched resistors and a priority encoder. The block diagram for the concept is provided below:

### Main Components of Flash ADC

Before understanding the working of the Flash ADC, we should have knowledge of its components.

### Resistor Voltage Divider Circuit

The resistive voltage divider as the name suggests is a simple circuit network of resistors connected in series with an input voltage to scale down its voltage. It happens because of the distribution of input voltage among all the resistors. This circuit is used to produce reference voltage or to step down the magnitude of a high voltage. The general formula for the circuit is derived using Kirchoff’s Laws.

If two resistors are connected in series then

`Vout= R2 x Vin / R1+R2`

### Comparator

The comparator is a basic operational amplifier that is used to either compare two analog voltages or an input voltage to a reference voltage. It then outputs a binary signal. The comparators are mostly a part of devices that need the digitization of their input voltage.

The working of a comparator is quite simple. The input voltage is connected to the positive end while the other voltage or the reference voltage is connected to the negative end of the comparator.

`If V+ > V- then Vout will be 1 and vout will be pulled low if V+ < V-.   `

### Priority Encoder

An encoder is a logic circuit that comes with 2 powered N inputs. It gives the binary code with respect to the corresponding high input. It produces errors if more than one input is at the high state. So, to counter this problem, The flash ADC is made using a priority encoder. The priority encoder does not produce ambiguous results even if two or more inputs are in a high state simultaneously. Instead, it delivers the binary code on the highest input priority basis. The priority mechanism can either be ascending or descending.

Let us have N number of inputs and consider Nth input as the highest priority input. If three inputs i.e N-1, 4, 2 are high at the same time then the priority encoder will generate a binary code corresponding to the N-1 input line.

## 3-Bit Flash ADC Example Circuit

To grasp the concept and better understanding it, we will study a 3-bit Flash ADC. A 3-bit Flash ADC consists of seven comparators, a resistive voltage divider circuit that contains 8 series resistors, and a priority encoder. The input analog voltage is applied to the positive terminal of the comparator while the reference voltage is applied to the negative end of the comparator.

Let us suppose that V1 is applied to the first comparator then this V1 can be calculated as

```V1= RxVref/R+7R
V1= Vref/8```

Now considering V2 as the reference voltage for comparator number 2. So the V2 would be

```V2= (R+R)xVref/8R
V2= 2Vref/8```

Similarly, by voltage dividing, we can find the reference voltages of each comparator.

• V3:                                            V3= 3Vref/8
• V4:                                            V4= 4Vref/8
• V5:                                            V5= 5Vref/8
• V6:                                            V6= 6Vref/8
• V7:                                            V7= 7Vref/8

These reference voltages of each comparator reveal that there is a difference of one least significant bit among each reference voltages.

`1 LSB= Vref/8`

Accordingly, each comparator compares the input voltage to the reference voltage. Here comes two cases.

If the input voltage is lesser than the reference voltage of the comparator then the output of the comparator is low. Whereas if the input voltage is greater than the reference voltage of the particular comparator then its output will be high.

The priority encoder is dependent on these comparators. The outputs of the comparators decide the binary code produced by the encoder.

To completely comprehend the working of the Flash ADC, we take an example reference and input voltage i.e. Vref=8V and Vin=3.3V respectively.

With the specific measurements, V1 turns out to be

```V1= Rx8V/R+7R
V1= 8Vf/8
V1= 1V```

All the reference voltages are calculated using the same voltage divider formula. Hence,

```V2= 3V
V3= 3V
V4= 4V
V5= 5V
V6= 6V
V7= 7V```

The analog input voltage is compared with all the comparators’ reference voltages of the Flash analog to digital converter. After comparison, we noticed that the reference voltages of the first three comparators i.e 1V, 2V, and 3V are less as compared to the input 3.3 V that is why the output of the first three comparators is high while the remaining comparators are at a low state.

These outputs are the inputs of the priority encoder. We can see that these reference voltages are seven in number so the 8th input line is connected to logic 1 and is given the least priority. It means that it is a descending order priority encoder. This helps in the case where all the comparators’ output voltages are zero. Hence the importance would be given to the higher priority outputs so the encoder generates an all-zero output.

As three input lines of the encoder are high at the same time, priority will be given to the third input and a corresponding output binary code is generated.

### Sample & Hold Circuit

This is the process through which a Flash analog to digital converter takes a continuous analog input and converts it into a binary output. For this ADC to be accurate, the input voltage must not vary otherwise it affects the output and produces errors. To tackle this, the Flash ADC is used in a combination with a sample and hold circuit. The respective circuit samples the input circuit and holds that sample circuit until the conversion is completed and the next signal arrives.

It is the optimized version of full flash ADC. The advantages of this configuration are that it requires less die area, less power consumption with the same resolution as the full flash ADC.

### Working Principle

Consider an 8-bit ADC. The schematic for the visual is as follows:

It consists of 2 4-bit Flash ADCs and a DAC in combination with a sample and holds a circuit and a subtractor. First, the sample & hold circuit samples the input voltage for the first 4-bit ADC. This ADC gives out the binary code which will be the MSB of the final binary output. It is fed into the DAC which converts the signal back to the analog signal to be used as a reference voltage. The output of the subtractor is the input of the second ADC and gives out the LSBs of the final binary output.

Therefore, the same resolution is achieved with only 30 comparators.

`2x (2^N-1)=30`

Though it has some genuine advantages, this configuration has a slow conversion speed compared to the full flash ADCs.

• It is the fastest ADC and is utilized in high bandwidth applications.