INTRODUCTION OF dsPIC DIGITAL SIGNAL CONTROLLER This article contains an introductory note at dsPIC as well as learn more about the features of this proficient digital signal controller. In 2001, Microchip introduced the dsPIC series of chips, which penetrated mass production later.They are Microchip’s first innately 16-bit microcontrollers. It is supported by embedded code.PIC24 devices are just designed as general function micro-controllers. dsPIC devices include digital signal processing (DSP) proficiencies in addition.The dsPIC is a 16-bit microcontroller with high-performance and the high computation speed of a fully implemented digital signal processor (DSP).It is for signal conditioning too. There are some features and motor control facility and peripherals in dsPIC to facilitate control applications and signal processing.
Introduction to dSPIC based DSC (Digital Signal Controller)
A Digital Signal Controller is a single-chip that flawlessly combines the control features of a Microcontroller (MCU) with the computation and throughput aptitudes of a Digital Signal Processor (DSP) just in a single core. Microchip’s dsPICR DSC offers you everything which would be expected from a powerful 16-bit MCU: sophisticated, fast and flexible interrupt handling; a wide array of analog and digital peripheral functions; flexible clocking options; power management; brown-out protection; power-on-reset; full-speed real-time emulation; code security; watchdog timer and full-speed in-circuit debug solutions.
By proficiently adding DSP capabilities to a high-performance 16-bit MCU.The dsPIC30F is an advanced 16-bit processor that offers accurate DSP capabilities with the fundamental real-time control proficiencies of a microcontroller.Extensive built-in peripherals, prioritize interrupts and power management features are joind with a full-featured DSP engine. Single-cycle 16×16 MAC, dual 40-bit accumulators, dual-operand fetches, 40-bit barrel shifter and zero-overhead looping are among the attributes that make this a very proficient DSC.
Special Features of dspic microcontrollers
- Flexible Flash:The dsPIC30F and dsPIC33F both make use of flexible and secure Flash memory. The dsPIC DSC Flash is used to store programs or data tables. All dsPIC DSCs can firmly self-program their own flash in a finished product.
- Add DSP: Adding a DSP chip in existing MCU-based system is complicated and costly. The dsPIC30F and the dsPIC33F are designed to feel and look like MCUs. Adding DSP functionalities in the familiar controller like environment can be completed easily.
- Powerful 16-bit MCU: The dsPIC30F and dsPIC33F families of digital signal controllers (DSC) execute most of the instructions in 1 cycle. It combines high instruction throughput with DSP capabilities, such as zero overhead looping and single cycle 16-bit multiply .
Architecture of dspic microcontrollers
The dsPIC processor (DSP) uses Harvard architecture with separate program and data memory buses, as shown in Figure Separate Data and Program Buses
This is an ability of Harvard architecture that it permits different size data (16 bits) and instruction (24 bits) words. This modified design improves the effectiveness of the instruction set. It also permits faster processing because the dsPIC processor (DSP) can pre-fetch the next instruction from program memory while it is executing the current instruction which accesses data RAM.
The Program Counter (PC) is 24 bits wide and it addresses up to 4M x 24 bits of user program memory space. The Program Counter can increments by 2 for each 24-bit instruction, which makes simpler the addressing of 16-bit data stored in program memory. Program memory space contains the Interrupt Vector Tables,Reset location, data EEPROM, user program memory and configuration memory.
The processor starts a program from the Reset location 0x000000. Program memory for the code initiates after the vector tables at address 0x100.
It should be user-programmed with GOTO instructions. The GOTO instructions at the Reset location are always followed by the Interrupt Vector Tables. Program looping is completed with least overhead with the DO and REPEAT
Instructions. These attributes make repetitive DSP algorithms very efficient while keeping up the talent to handle real-time events.
Data Addressing Modes of dspic
The CPU supports Relative, Memory Direct, Literal, Register Direct and Register Indirect Addressing modes. Each instruction that addresses data memory can use some of the available addressing modes and almost 6 addressing modes are available to support each instruction. The working registers are used widely as address pointers for the indirect addressing modes. They can be modified or incremented and used as pointers in the same instruction.
The features of DSP engine are high-speed, multiplier, 17-bit x 17-bit fixed-point, a 40-bit ALU (Arithmetic Logic Unit), a 40-bit bidirectional barrel shifter and two 40-bit saturating accumulators. In it, barrel shifter has capability of shifting a 40-bit value up to 15 bits right or may up to 16 bits left, in one single cycle.The DSP instructions operate with all other instructions seamlessly and have been accurately designed for most favourable real-time performance. The MAC and other associated instructions concurrently fetch two data operands from memory at the time of multiplying two W registers.
Peripherals of dspic microcontrollers
These devices (dsPIC) are obtainable with a wide range of peripherals. The main peripherals include:
I/O Ports 10-bit or 12-bit A/D Converter
Output Compare/PWM I2C.
Input Capture SPI.
Motor Control PWM Data Converter (CODEC)Interface
Controller Area Network (CAN) Quadrature Encoder
Interrupts of dspic microcontrollers
The dsPIC30F has a vectored interrupt system. Each interrupt has its own vector and can be assigned one of seven priority levels. Each interrupt vector contains starting address 24bit wide of the associated Interrupt Service Routine (ISR).The interrupt entry and return latencies are always providing deterministic timing for real-time applications and fixed. The Interrupt Vector Table (IVT) exists in program memory.The Interrupt Vector Table ( IVT) contains 62 vectors containing up to 8 non-mark able error trap vectors and up to 55 sources of the interrupt.